The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device having a redundant circuit.
Recently, the memory capacity of semiconductor memory devices have increased considerably, and in order to improve the production yield of mask read only memories (ROMs), for example, a redundant circuit is provided in the semiconductor memory device. In the redundant circuit, redundant cells for storing correction data are provided in addition to normal memory cells, and defective cells are compensated by the redundant cells.
FIG. 1 is a plan view showing a general mask ROM. In a mask ROM 100 shown in FIG. 1, a memory cell array, a column decoder, a row decoder, a sense amplifier and the like are provided in an element region 101. A part 102 of the element region 101 is shown on an enlarged scale in FIG. 2 in the form of a block diagram.
In FIG. 2, the part 102 generally includes a circuit portion 111 provided with respect to an upper address, and a circuit portion 112 provided with respect to a lower address. In other words, since the memory capacity of this mask ROM 100 is large, the memory cell array is divided into upper address memory cells for the upper address and lower address memory cells for the lower address. Accordingly, if an input address is greater than a predetermined value, for example, an access is made to the upper address memory cells from the circuit portion 111. In this example, the mask ROM 100 employs a 16-bit parity system.
The circuit portion 111 includes upper address memory cell arrays 01H and 05H, a sense amplifier 111-1 provided with respect to the memory cell array 01H, a column decoder 111-2 provided with respect to the memory cell array 01H, a sense amplifier 111-3 provided with respect to the memory cell array 05H, a column decoder 111-4 provided with respect to the memory cell array 05H, a redundant cell array 111-5 for storing correction data for the upper address, a sense amplifier 111-6 provided with respect to the redundant cell array 111-5, a column decoder 111-7 provided with respect to the redundant cell array 111-5, a row decoder 111-8 provided with respect to the memory cell array 01H, a row decoder 111-9 provided with respect to the memory cell array 05H, and a row decoder 111-10 provided with respect to the redundant cell array 111-5.
Similarly, the circuit portion 112 includes lower address memory cell arrays 01L and 05L, a sense amplifier 112-1 provided with respect to the memory cell array 05L, a column decoder 112-2 provided with respect to the memory cell array 05L, a sense amplifier 112-3 provided with respect to the memory cell array 01L, a column decoder 112-4 provided with respect to the memory cell array 01L, a redundant cell array 112-5 for storing correction data for the lower address, a sense amplifier 112-6 provided with respect to the redundant cell array 112-5, a column decoder 112-7 provided with respect to the redundant cell array 112-5, a row decoder 112-8 provided with respect to the memory cell array 05L, a row decoder 112-9 provided with respect to the memory cell array 01L, and a row decoder 112-10 provided with respect to the redundant cell array 112-5.
In FIG. 2, BL denotes a bit line, WDXX denotes a word system input, RDECOX through RDEC2X denote row decoder selection lines, BSBXX denotes a block system input, BLC denotes a bit line exclusively for correction data, and RDSC denotes a row decoder selection line exclusively for the correction data.
However, according to the structure shown in FIG. 2, the sense amplifier 111-6, the column decoder 111-7 and the row decoder 111-10 are provided exclusively with respect to the redundant cell array 111-5. Similarly, the sense amplifier 112-6, the column decoder 112-7 and the row decoder 112-10 are provided exclusively with respect to the redundant cell array 112-5. In addition, the bit lines BLC and the row decoder selection lines RDSC exclusively for the correction data are provided with respect to the redundant cell arrays 111-5 and 112-5.
For this reason, the sense amplifiers 111-6 and 112-6, the column decoders 111-7 and 112-7, the row decoders 111-10 and 112-10, the bit lines BLC and the row decoder selection lines RDSC which are provided exclusively with respect to the redundant cell arrays 111-5 and 112-5 occupy a relatively large area on the element region 101 shown in FIG. 1, thereby preventing further improvement in the integration density of the mask ROM 100. In other words, when increasing the memory capacity of the mask ROM, it is essential to provide redundant cells in order to improve the production yield, however, it becomes necessary to provide circuits such as sense amplifiers and column decoders exclusively for the redundant cells, and consequently, there was a limit to improving the integration density of the mask ROM.
On the other hand, because the sense amplifiers 111-6 and 112-6, the column decoders 111-7 and 112-7, and the row decoders 111-10 and 112-10 are provided exclusively with respect to the redundant cell arrays 111-5 and 112-5, the power consumption of these parts and the power consumption of a drive and control system for driving and controlling these parts are added to the total power consumption of the mask ROM 100. Therefore, there was a limit to reducing the power consumption of the mask ROM.